11#include "hardware/structs/dma.h"
12#include "hardware/regs/dreq.h"
13#include "pico/assert.h"
14#include "hardware/regs/intctrl.h"
39#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_DMA
40#ifdef PARAM_ASSERTIONS_ENABLED_DMA
41#define PARAM_ASSERTIONS_ENABLED_HARDWARE_DMA PARAM_ASSERTIONS_ENABLED_DMA
43#define PARAM_ASSERTIONS_ENABLED_HARDWARE_DMA 0
56#define DMA_IRQ_NUM(irq_index) (DMA_IRQ_0 + (irq_index))
59static inline void check_dma_channel_param(__unused uint channel) {
60#if PARAM_ASSERTIONS_ENABLED(HARDWARE_DMA)
62 extern void check_dma_channel_param_impl(uint channel);
63 check_dma_channel_param_impl(channel);
67static inline void check_dma_timer_param(__unused uint timer_num) {
68 valid_params_if(HARDWARE_DMA, timer_num < NUM_DMA_TIMERS);
72 check_dma_channel_param(channel);
73 return &dma_hw->ch[channel];
161 c->ctrl = incr ? (c->ctrl | DMA_CH0_CTRL_TRIG_INCR_READ_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_INCR_READ_BITS);
172 c->ctrl = incr ? (c->ctrl | DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS);
192 c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS) | (dreq << DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB);
205 assert(chain_to <= NUM_DMA_CHANNELS);
206 c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS) | (chain_to << DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB);
220 c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS) | (((uint)size) << DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB);
239 assert(size_bits < 32);
240 c->ctrl = (c->ctrl & ~(DMA_CH0_CTRL_TRIG_RING_SIZE_BITS | DMA_CH0_CTRL_TRIG_RING_SEL_BITS)) |
241 (size_bits << DMA_CH0_CTRL_TRIG_RING_SIZE_LSB) |
242 (write ? DMA_CH0_CTRL_TRIG_RING_SEL_BITS : 0);
255 c->ctrl = bswap ? (c->ctrl | DMA_CH0_CTRL_TRIG_BSWAP_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_BSWAP_BITS);
269 c->ctrl = irq_quiet ? (c->ctrl | DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS);
287 c->ctrl = high_priority ? (c->ctrl | DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS);
302 c->ctrl = enable ? (c->ctrl | DMA_CH0_CTRL_TRIG_EN_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_EN_BITS);
314 c->ctrl = sniff_enable ? (c->ctrl | DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS) : (c->ctrl &
315 ~DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS);
362 c.ctrl = dma_channel_hw_addr(channel)->ctrl_trig;
401 dma_channel_hw_addr(channel)->read_addr = (uintptr_t) read_addr;
403 dma_channel_hw_addr(channel)->al3_read_addr_trig = (uintptr_t) read_addr;
416 dma_channel_hw_addr(channel)->write_addr = (uintptr_t) write_addr;
418 dma_channel_hw_addr(channel)->al2_write_addr_trig = (uintptr_t) write_addr;
431 dma_channel_hw_addr(channel)->transfer_count = trans_count;
433 dma_channel_hw_addr(channel)->al1_transfer_count_trig = trans_count;
448 const volatile void *read_addr,
449 uint transfer_count,
bool trigger) {
464 const volatile void *read_addr,
465 uint32_t transfer_count) {
468 hw->read_addr = (uintptr_t) read_addr;
469 hw->al1_transfer_count_trig = transfer_count;
481 hw->write_addr = (uintptr_t) write_addr;
482 hw->al1_transfer_count_trig = transfer_count;
491 valid_params_if(HARDWARE_DMA, chan_mask && chan_mask < (1u << NUM_DMA_CHANNELS));
492 dma_hw->multi_channel_trigger = chan_mask;
545 check_dma_channel_param(channel);
546 dma_hw->abort = 1u << channel;
559 check_dma_channel_param(channel);
560 check_hw_layout(
dma_hw_t, inte0, DMA_INTE0_OFFSET);
588 check_dma_channel_param(channel);
589 check_hw_layout(
dma_hw_t, inte1, DMA_INTE1_OFFSET);
618 invalid_params_if(HARDWARE_DMA, irq_index >= NUM_DMA_IRQS);
621 hw_set_bits(&dma_hw->irq_ctrl[irq_index].inte, 1u << channel);
623 hw_clear_bits(&dma_hw->irq_ctrl[irq_index].inte, 1u << channel);
634 invalid_params_if(HARDWARE_DMA, irq_index >= NUM_DMA_IRQS);
636 hw_set_bits(&dma_hw->irq_ctrl[irq_index].inte, channel_mask);
638 hw_clear_bits(&dma_hw->irq_ctrl[irq_index].inte, channel_mask);
649 check_dma_channel_param(channel);
650 return dma_hw->ints0 & (1u << channel);
660 check_dma_channel_param(channel);
661 return dma_hw->ints1 & (1u << channel);
672 invalid_params_if(HARDWARE_DMA, irq_index >= NUM_DMA_IRQS);
673 check_dma_channel_param(channel);
674 return dma_hw->irq_ctrl[irq_index].ints & (1u << channel);
683 check_dma_channel_param(channel);
684 dma_hw->ints0 = 1u << channel;
693 check_dma_channel_param(channel);
694 dma_hw->ints1 = 1u << channel;
704 invalid_params_if(HARDWARE_DMA, irq_index >= NUM_DMA_IRQS);
705 check_dma_channel_param(channel);
706 dma_hw->irq_ctrl[irq_index].ints = 1u << channel;
716 check_dma_channel_param(channel);
717 return dma_hw->ch[channel].al1_ctrl & DMA_CH0_CTRL_TRIG_BUSY_BITS;
752 check_dma_channel_param(channel);
753 check_hw_layout(
dma_hw_t, sniff_ctrl, DMA_SNIFF_CTRL_OFFSET);
754 if (force_channel_enable) {
755 hw_set_bits(&dma_hw->ch[channel].al1_ctrl, DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS);
758 (((channel << DMA_SNIFF_CTRL_DMACH_LSB) & DMA_SNIFF_CTRL_DMACH_BITS) |
759 ((mode << DMA_SNIFF_CTRL_CALC_LSB) & DMA_SNIFF_CTRL_CALC_BITS) |
760 DMA_SNIFF_CTRL_EN_BITS),
761 (DMA_SNIFF_CTRL_DMACH_BITS |
762 DMA_SNIFF_CTRL_CALC_BITS |
763 DMA_SNIFF_CTRL_EN_BITS));
779 hw_set_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_BSWAP_BITS);
781 hw_clear_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_BSWAP_BITS);
794 hw_set_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_OUT_INV_BITS);
796 hw_clear_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_OUT_INV_BITS);
809 hw_set_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_OUT_REV_BITS);
811 hw_clear_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_OUT_REV_BITS);
819 dma_hw->sniff_ctrl = 0;
831 dma_hw->sniff_data = seed_value;
840 return dma_hw->sniff_data;
892 check_dma_timer_param(timer);
893 invalid_params_if(HARDWARE_DMA, numerator > denominator);
894 dma_hw->timer[timer] = (((uint32_t)numerator) << DMA_TIMER0_X_LSB) | (((uint32_t)denominator) << DMA_TIMER0_Y_LSB);
906 check_dma_timer_param(timer_num);
917 valid_params_if(HARDWARE_DMA, irq_index < NUM_DMA_IRQS);
static void channel_config_set_high_priority(dma_channel_config *c, bool high_priority)
Set the channel priority in a channel configuration object.
Definition dma.h:286
static void channel_config_set_read_increment(dma_channel_config *c, bool incr)
Set DMA channel read increment in a channel configuration object.
Definition dma.h:160
static dma_channel_config dma_get_channel_config(uint channel)
Get the current configuration for the specified channel.
Definition dma.h:360
static dma_channel_config dma_channel_get_default_config(uint channel)
Get the default channel configuration for a given channel.
Definition dma.h:338
static void channel_config_set_bswap(dma_channel_config *c, bool bswap)
Set DMA byte swapping config in a channel configuration object.
Definition dma.h:254
static void channel_config_set_sniff_enable(dma_channel_config *c, bool sniff_enable)
Enable access to channel by sniff hardware in a channel configuration object.
Definition dma.h:313
static void channel_config_set_dreq(dma_channel_config *c, uint dreq)
Select a transfer request signal in a channel configuration object.
Definition dma.h:190
static void channel_config_set_chain_to(dma_channel_config *c, uint chain_to)
Set DMA channel chain_to channel in a channel configuration object.
Definition dma.h:204
static uint32_t channel_config_get_ctrl_value(const dma_channel_config *config)
Get the raw configuration register from a channel configuration.
Definition dma.h:372
static void channel_config_set_write_increment(dma_channel_config *c, bool incr)
Set DMA channel write increment in a channel configuration object.
Definition dma.h:171
static void channel_config_set_irq_quiet(dma_channel_config *c, bool irq_quiet)
Set IRQ quiet mode in a channel configuration object.
Definition dma.h:268
static void channel_config_set_enable(dma_channel_config *c, bool enable)
Enable/Disable the DMA channel in a channel configuration object.
Definition dma.h:301
static void channel_config_set_transfer_data_size(dma_channel_config *c, enum dma_channel_transfer_size size)
Set the size of each DMA bus transfer in a channel configuration object.
Definition dma.h:218
static void channel_config_set_ring(dma_channel_config *c, bool write, uint size_bits)
Set address wrapping parameters in a channel configuration object.
Definition dma.h:238
static __force_inline void hw_set_bits(io_rw_32 *addr, uint32_t mask)
Atomically set the specified bits to 1 in a HW register.
Definition address_mapped.h:135
static __force_inline void hw_write_masked(io_rw_32 *addr, uint32_t values, uint32_t write_mask)
Set new values for a sub-set of the bits in a HW register.
Definition address_mapped.h:171
static __force_inline void hw_clear_bits(io_rw_32 *addr, uint32_t mask)
Atomically clear the specified bits to 0 in a HW register.
Definition address_mapped.h:145
void dma_unclaim_mask(uint32_t channel_mask)
Mark multiple dma channels as no longer used.
Definition dma.c:39
static void dma_sniffer_enable(uint channel, uint mode, bool force_channel_enable)
Enable the DMA sniffing targeting the specified channel.
Definition dma.h:751
void dma_timer_claim(uint timer)
Mark a dma timer as used.
Definition dma.c:54
static void dma_sniffer_set_output_invert_enabled(bool invert)
Enable the Sniffer output invert function.
Definition dma.h:792
static void dma_channel_set_trans_count(uint channel, uint32_t trans_count, bool trigger)
Set the number of bus transfers the channel will do.
Definition dma.h:429
int dma_claim_unused_timer(bool required)
Claim a free dma timer.
Definition dma.c:64
static uint32_t dma_sniffer_get_data_accumulator(void)
Get the sniffer's data accumulator value.
Definition dma.h:839
static void dma_channel_start(uint channel)
Start a single DMA channel.
Definition dma.h:500
static bool dma_irqn_get_channel_status(uint irq_index, uint channel)
Determine if a particular channel is a cause of DMA_IRQ_N.
Definition dma.h:671
int dma_claim_unused_channel(bool required)
Claim a free dma channel.
Definition dma.c:45
static void dma_channel_acknowledge_irq1(uint channel)
Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_1.
Definition dma.h:692
static void dma_channel_set_irq1_enabled(uint channel, bool enabled)
Enable single DMA channel's interrupt via DMA_IRQ_1.
Definition dma.h:587
static void dma_timer_set_fraction(uint timer, uint16_t numerator, uint16_t denominator)
Set the multiplier for the given DMA timer.
Definition dma.h:891
static int dma_get_irq_num(uint irq_index)
Return DMA_IRQ_<irqn>
Definition dma.h:916
static void dma_start_channel_mask(uint32_t chan_mask)
Start one or more channels simultaneously.
Definition dma.h:490
void dma_channel_cleanup(uint channel)
Performs DMA channel cleanup after use.
Definition dma.c:73
#define DMA_IRQ_NUM(irq_index)
Returns the irq_num_t for the nth DMA interrupt.
Definition dma.h:56
static void dma_irqn_set_channel_enabled(uint irq_index, uint channel, bool enabled)
Enable single DMA channel interrupt on either DMA_IRQ_0 or DMA_IRQ_1.
Definition dma.h:617
static void dma_irqn_set_channel_mask_enabled(uint irq_index, uint32_t channel_mask, bool enabled)
Enable multiple DMA channels' interrupt via either DMA_IRQ_0 or DMA_IRQ_1.
Definition dma.h:633
static void dma_channel_abort(uint channel)
Stop a DMA transfer.
Definition dma.h:544
static void dma_channel_set_config(uint channel, const dma_channel_config *config, bool trigger)
Set a channel configuration.
Definition dma.h:383
static uint dma_get_timer_dreq(uint timer_num)
Return the DREQ number for a given DMA timer.
Definition dma.h:902
void dma_timer_unclaim(uint timer)
Mark a dma timer as no longer used.
Definition dma.c:59
static void dma_channel_transfer_to_buffer_now(uint channel, volatile void *write_addr, uint32_t transfer_count)
Start a DMA transfer to a buffer immediately.
Definition dma.h:479
static void dma_channel_configure(uint channel, const dma_channel_config *config, volatile void *write_addr, const volatile void *read_addr, uint transfer_count, bool trigger)
Configure all DMA parameters and optionally start transfer.
Definition dma.h:447
bool dma_channel_is_claimed(uint channel)
Determine if a dma channel is claimed.
Definition dma.c:49
bool dma_timer_is_claimed(uint timer)
Determine if a dma timer is claimed.
Definition dma.c:68
static void dma_sniffer_disable(void)
Disable the DMA sniffer.
Definition dma.h:818
static void dma_sniffer_set_output_reverse_enabled(bool reverse)
Enable the Sniffer output bit reversal function.
Definition dma.h:807
void dma_claim_mask(uint32_t channel_mask)
Mark multiple dma channels as used.
Definition dma.c:28
static bool dma_channel_get_irq0_status(uint channel)
Determine if a particular channel is a cause of DMA_IRQ_0.
Definition dma.h:648
static void dma_set_irq1_channel_mask_enabled(uint32_t channel_mask, bool enabled)
Enable multiple DMA channels' interrupts via DMA_IRQ_1.
Definition dma.h:602
static void dma_channel_wait_for_finish_blocking(uint channel)
Wait for a DMA channel transfer to complete.
Definition dma.h:725
static void dma_channel_transfer_from_buffer_now(uint channel, const volatile void *read_addr, uint32_t transfer_count)
Start a DMA transfer from a buffer immediately.
Definition dma.h:463
static void dma_channel_set_read_addr(uint channel, const volatile void *read_addr, bool trigger)
Set the DMA initial read address.
Definition dma.h:399
static void dma_sniffer_set_byte_swap_enabled(bool swap)
Enable the Sniffer byte swap function.
Definition dma.h:777
void dma_channel_unclaim(uint channel)
Mark a dma channel as no longer used.
Definition dma.c:34
static void dma_sniffer_set_data_accumulator(uint32_t seed_value)
Set the sniffer's data accumulator with initial value.
Definition dma.h:830
dma_channel_transfer_size
Enumeration of available DMA channel transfer sizes.
Definition dma.h:143
static void dma_irqn_acknowledge_channel(uint irq_index, uint channel)
Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_N.
Definition dma.h:703
static void dma_set_irq0_channel_mask_enabled(uint32_t channel_mask, bool enabled)
Enable multiple DMA channels' interrupts via DMA_IRQ_0.
Definition dma.h:573
void dma_channel_claim(uint channel)
Mark a dma channel as used.
Definition dma.c:23
static void dma_channel_set_write_addr(uint channel, volatile void *write_addr, bool trigger)
Set the DMA initial write address.
Definition dma.h:414
static void dma_channel_set_irq0_enabled(uint channel, bool enabled)
Enable single DMA channel's interrupt via DMA_IRQ_0.
Definition dma.h:558
static bool dma_channel_get_irq1_status(uint channel)
Determine if a particular channel is a cause of DMA_IRQ_1.
Definition dma.h:659
static bool dma_channel_is_busy(uint channel)
Check if DMA channel is busy.
Definition dma.h:715
static void dma_channel_acknowledge_irq0(uint channel)
Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_0.
Definition dma.h:682
@ DREQ_DMA_TIMER1
Select DMA_TIMER0 as DREQ.
Definition dreq.h:108
@ DREQ_DMA_TIMER0
Select DMA_TIMER0 as DREQ.
Definition dreq.h:107
@ DREQ_DMA_TIMER3
Select DMA_TIMER3 as DREQ.
Definition dreq.h:110
@ DREQ_DMA_TIMER2
Select DMA_TIMER1 as DREQ.
Definition dreq.h:109
@ DREQ_FORCE
Select FORCE as DREQ.
Definition dreq.h:111
@ DMA_SIZE_16
Half word transfer (16 bits)
Definition dma.h:145
@ DMA_SIZE_8
Byte transfer (8 bits)
Definition dma.h:144
@ DMA_SIZE_32
Word transfer (32 bits)
Definition dma.h:146