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cyw43_driver.h
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1/*
2 * Copyright (c) 2022 Raspberry Pi (Trading) Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef _PICO_CYW43_DRIVER_H
8#define _PICO_CYW43_DRIVER_H
9
17#include "pico.h"
18
19#if CYW43_PIN_WL_DYNAMIC
20#include "cyw43_configport.h"
21#endif
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27struct async_context;
28
37bool cyw43_driver_init(struct async_context *context);
38
44void cyw43_driver_deinit(struct async_context *context);
45
46// PICO_CONFIG: CYW43_PIO_CLOCK_DIV_DYNAMIC, Enable runtime configuration of the clock divider for communication with the wireless chip, type=bool, default=0, group=pico_cyw43_driver
47#ifndef CYW43_PIO_CLOCK_DIV_DYNAMIC
48#define CYW43_PIO_CLOCK_DIV_DYNAMIC 0
49#endif
50
51// PICO_CONFIG: CYW43_PIO_CLOCK_DIV_INT, Integer part of the clock divider for communication with the wireless chip, type=int, default=2, group=pico_cyw43_driver
52#ifndef CYW43_PIO_CLOCK_DIV_INT
53// backwards compatibility using old define
54#ifdef CYW43_PIO_CLOCK_DIV
55#define CYW43_PIO_CLOCK_DIV_INT CYW43_PIO_CLOCK_DIV
56#else
57#define CYW43_PIO_CLOCK_DIV_INT 2
58#endif
59#endif
60
61// PICO_CONFIG: CYW43_PIO_CLOCK_DIV_FRAC8, Fractional part of the clock divider for communication with the wireless chip 0-255, type=int, min=0, max=255, default=0, group=pico_cyw43_driver
62#ifndef CYW43_PIO_CLOCK_DIV_FRAC8
63#ifdef CYW43_PIO_CLOCK_DIV_FRAC
64#define CYW43_PIO_CLOCK_DIV_FRAC8 CYW43_PIO_CLOCK_DIV_FRAC
65#else
66#define CYW43_PIO_CLOCK_DIV_FRAC8 0
67#endif
68#endif
69
70// PICO_CONFIG: CYW43_PIN_WL_DYNAMIC, flag to indicate if cyw43 SPI pins can be changed at runtime, type=bool, advanced=true, group=pico_cyw43_driver
71
72// PICO_CONFIG: CYW43_DEFAULT_PIN_WL_REG_ON, gpio pin to power up the cyw43 chip, type=int, min=0, max=47 on RP2350B, 29 otherwise, advanced=true, group=pico_cyw43_driver
73
74// PICO_CONFIG: CYW43_DEFAULT_PIN_WL_DATA_OUT, gpio pin for spi data out to the cyw43 chip, type=int, min=0, max=47 on RP2350B, 29 otherwise, advanced=true, group=pico_cyw43_driver
75
76// PICO_CONFIG: CYW43_DEFAULT_PIN_WL_DATA_IN, gpio pin for spi data in from the cyw43 chip, type=int, min=0, max=47 on RP2350B, 29 otherwise, advanced=true, group=pico_cyw43_driver
77
78// PICO_CONFIG: CYW43_DEFAULT_PIN_WL_HOST_WAKE, gpio (irq) pin for the irq line from the cyw43 chip, type=int, min=0, max=47 on RP2350B, 29 otherwise, advanced=true, group=pico_cyw43_driver
79
80// PICO_CONFIG: CYW43_DEFAULT_PIN_WL_CLOCK, gpio pin for the spi clock line to the cyw43 chip, type=int, min=0, max=47 on RP2350B, 29 otherwise, advanced=true, group=pico_cyw43_driver
81
82// PICO_CONFIG: CYW43_DEFAULT_PIN_WL_CS, gpio pin for the spi chip select to the cyw43 chip, type=int, min=0, max=47 on RP2350B, 29 otherwise, advanced=true, group=pico_cyw43_driver
83
84#if CYW43_PIO_CLOCK_DIV_DYNAMIC
95void cyw43_set_pio_clkdiv_int_frac8(uint32_t clock_div_int, uint8_t clock_div_frac8);
96
97// backwards compatibility
98static inline void cyw43_set_pio_clock_divisor(uint16_t clock_div_int, uint8_t clock_div_frac8) {
99 return cyw43_set_pio_clkdiv_int_frac8(clock_div_int, clock_div_frac8);
100}
101#endif
102
103#if CYW43_PIN_WL_DYNAMIC
115int cyw43_set_pins_wl(uint pins[CYW43_PIN_INDEX_WL_COUNT]);
116#endif
117
118#ifdef __cplusplus
119}
120#endif
121#endif
bool cyw43_driver_init(struct async_context *context)
Initializes the lower level cyw43_driver and integrates it with the provided async_context.
Definition cyw43_driver.c:106
void cyw43_driver_deinit(struct async_context *context)
De-initialize the lowever level cyw43_driver and unhooks it from the async_context.
Definition cyw43_driver.c:116
Base structure type of all async_contexts. For details about its use, see pico_async_context.
Definition async_context.h:179