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irq.h
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1/*
2 * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef _HARDWARE_IRQ_H
8#define _HARDWARE_IRQ_H
9
10// These two config items are also used by assembler, so keeping separate
11// PICO_CONFIG: PICO_MAX_SHARED_IRQ_HANDLERS, Maximum number of shared IRQ handlers, default=4, advanced=true, group=hardware_irq
12#ifndef PICO_MAX_SHARED_IRQ_HANDLERS
13#define PICO_MAX_SHARED_IRQ_HANDLERS 4
14#endif
15
16// PICO_CONFIG: PICO_DISABLE_SHARED_IRQ_HANDLERS, Disable shared IRQ handlers, type=bool, default=0, group=hardware_irq
17#ifndef PICO_DISABLE_SHARED_IRQ_HANDLERS
18#define PICO_DISABLE_SHARED_IRQ_HANDLERS 0
19#endif
20
21// PICO_CONFIG: PICO_VTABLE_PER_CORE, User is using separate vector tables per core, type=bool, default=0, group=hardware_irq
22#ifndef PICO_VTABLE_PER_CORE
23#define PICO_VTABLE_PER_CORE 0
24#endif
25
26#ifndef __ASSEMBLER__
27
28#include "pico.h"
30#include "hardware/regs/intctrl.h"
31
32#include "pico/platform/cpu_regs.h"
33
161// PICO_CONFIG: PICO_DEFAULT_IRQ_PRIORITY, Define the default IRQ priority, default=0x80, group=hardware_irq
162#ifndef PICO_DEFAULT_IRQ_PRIORITY
163#define PICO_DEFAULT_IRQ_PRIORITY 0x80
164#endif
165
166#define PICO_LOWEST_IRQ_PRIORITY 0xff
167#define PICO_HIGHEST_IRQ_PRIORITY 0x00
168
169// PICO_CONFIG: PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY, Set default shared IRQ order priority, default=0x80, group=hardware_irq
170#ifndef PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY
171#define PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY 0x80
172#endif
173
174#define PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY 0xff
175#define PICO_SHARED_IRQ_HANDLER_LOWEST_ORDER_PRIORITY 0x00
176
177// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ, Enable/disable assertions in the hardware_irq module, type=bool, default=0, group=hardware_irq
178#ifndef PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ
179#ifdef PARAM_ASSERTIONS_ENABLED_IRQ // backwards compatibility with SDK < 2.0.0
180#define PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ PARAM_ASSERTIONS_ENABLED_IRQ
181#else
182#define PARAM_ASSERTIONS_ENABLED_HARDWARE_IRQ 0
183#endif
184#endif
185
186#ifdef __cplusplus
187extern "C" {
188#endif
189
195typedef void (*irq_handler_t)(void);
196
197static inline void check_irq_param(__unused uint num) {
198 invalid_params_if(HARDWARE_IRQ, num >= NUM_IRQS);
199}
200
221void irq_set_priority(uint num, uint8_t hardware_priority);
222
244uint irq_get_priority(uint num);
245
252void irq_set_enabled(uint num, bool enabled);
253
260bool irq_is_enabled(uint num);
261
268void irq_set_mask_enabled(uint32_t mask, bool enabled);
269
277void irq_set_mask_n_enabled(uint n, uint32_t mask, bool enabled);
278
320void irq_set_exclusive_handler(uint num, irq_handler_t handler);
321
334
386void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_priority);
387
404void irq_remove_handler(uint num, irq_handler_t handler);
405
415bool irq_has_handler(uint num);
416
426bool irq_has_shared_handler(uint num);
427
436
446static inline void irq_clear(uint int_num) {
447#if PICO_RP2040
448 *((volatile uint32_t *) (PPB_BASE + M0PLUS_NVIC_ICPR_OFFSET)) = (1u << ((uint32_t) (int_num & 0x1F)));
449#elif defined(__riscv)
450 // External IRQs are not latched, but we should clear the IRQ force bit here
451 hazard3_irqarray_clear(RVCSR_MEIFA_OFFSET, int_num / 16, 1u << (int_num % 16));
452#else
453 nvic_hw->icpr[int_num/32] = 1 << (int_num % 32);
454#endif
455}
456
464void irq_set_pending(uint num);
465
466
472
473static __force_inline void irq_init_priorities(void) {
475}
476
489void user_irq_claim(uint irq_num);
490
505void user_irq_unclaim(uint irq_num);
506
520int user_irq_claim_unused(bool required);
521
522/*
523*! \brief Check if a user IRQ is in use on the calling core
524 * \ingroup hardware_irq
525 *
526 * User IRQs starting from FIRST_USER_IRQ are not connected to any hardware, but can be triggered by \ref irq_set_pending.
527 *
528 * \note User IRQs are a core local feature; they cannot be used to communicate between cores. Therefore all functions
529 * dealing with Uer IRQs affect only the calling core
530 *
531 * \param irq_num the irq irq_num
532 * \return true if the irq_num is claimed, false otherwise
533 * \sa user_irq_claim
534 * \sa user_irq_unclaim
535 * \sa user_irq_claim_unused
536 */
537bool user_irq_is_claimed(uint irq_num);
538
539void __unhandled_user_irq(void);
540
541#ifdef __riscv
542enum riscv_vector_num {
543 RISCV_VEC_MACHINE_EXCEPTION = 0,
544 RISCV_VEC_MACHINE_SOFTWARE_IRQ = 3,
545 RISCV_VEC_MACHINE_TIMER_IRQ = 7,
546 RISCV_VEC_MACHINE_EXTERNAL_IRQ = 11,
547};
548
549irq_handler_t irq_set_riscv_vector_handler(enum riscv_vector_num index, irq_handler_t handler);
550#endif
551
552#if PICO_SECURE
553static inline void irq_assign_to_ns(uint irq_num, bool ns) {
554 check_irq_param(irq_num);
555 if (ns) nvic_hw->itns[irq_num >> 5] |= 1u << (irq_num & 0x1fu);
556 else nvic_hw->itns[irq_num >> 5] &= ~(1u << (irq_num & 0x1fu));
557}
558#endif
559#ifdef __cplusplus
560}
561#endif
562
563#endif
564#endif
bool irq_is_enabled(uint num)
Determine if a specific interrupt is enabled on the executing core.
Definition irq.c:67
void user_irq_unclaim(uint irq_num)
Mark a user IRQ as no longer used on the calling core.
Definition irq.c:685
static void irq_clear(uint int_num)
Clear a specific interrupt on the executing core.
Definition irq.h:446
void irq_set_pending(uint num)
Force an interrupt to be pending on the executing core.
Definition irq.c:117
irq_handler_t irq_get_exclusive_handler(uint num)
Get the exclusive interrupt handler for an interrupt on the executing core.
Definition irq.c:238
irq_handler_t irq_get_vtable_handler(uint num)
Get the current IRQ handler for the specified IRQ from the currently installed hardware vector table ...
Definition irq.c:220
uint irq_get_priority(uint num)
Get specified interrupt's priority.
Definition irq.c:610
void irq_set_enabled(uint num, bool enabled)
Enable or disable a specific interrupt on the executing core.
Definition irq.c:61
void(* irq_handler_t)(void)
Interrupt handler function type.
Definition irq.h:195
bool irq_has_handler(uint num)
Determine if there is an installed IRQ handler for the given interrupt number.
Definition irq.c:200
void user_irq_claim(uint irq_num)
Claim ownership of a user IRQ on the calling core.
Definition irq.c:681
int user_irq_claim_unused(bool required)
Claim ownership of a free user IRQ on the calling core.
Definition irq.c:689
void irq_set_priority(uint num, uint8_t hardware_priority)
Set specified interrupt's priority.
Definition irq.c:593
void irq_remove_handler(uint num, irq_handler_t handler)
Remove a specific interrupt handler for the given irq number on the executing core.
Definition irq.c:476
void irq_set_mask_n_enabled(uint n, uint32_t mask, bool enabled)
Enable/disable multiple interrupts on the executing core.
Definition irq.c:113
bool irq_has_shared_handler(uint num)
Determine if the current IRQ andler for the given interrupt number is shared.
Definition irq.c:206
void irq_set_mask_enabled(uint32_t mask, bool enabled)
Enable/disable multiple interrupts on the executing core.
Definition irq.c:109
void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_priority)
Add a shared interrupt handler for an interrupt on the executing core.
Definition irq.c:362
void irq_set_exclusive_handler(uint num, irq_handler_t handler)
Set an exclusive interrupt handler for an interrupt on the executing core.
Definition irq.c:225
#define __force_inline
Attribute to force inlining of a function regardless of optimization level.
Definition compiler.h:125
void runtime_init_per_core_irq_priorities(void)
Perform IRQ priority initialization for the current core.
Definition irq.c:657