28 _REG_(DMA_CH0_READ_ADDR_OFFSET)
33 _REG_(DMA_CH0_WRITE_ADDR_OFFSET)
38 _REG_(DMA_CH0_TRANS_COUNT_OFFSET)
41 io_rw_32 transfer_count;
43 _REG_(DMA_CH0_CTRL_TRIG_OFFSET)
63 _REG_(DMA_CH0_AL1_CTRL_OFFSET)
68 _REG_(DMA_CH0_AL1_READ_ADDR_OFFSET)
71 io_rw_32 al1_read_addr;
73 _REG_(DMA_CH0_AL1_WRITE_ADDR_OFFSET)
76 io_rw_32 al1_write_addr;
78 _REG_(DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET)
81 io_rw_32 al1_transfer_count_trig;
83 _REG_(DMA_CH0_AL2_CTRL_OFFSET)
88 _REG_(DMA_CH0_AL2_TRANS_COUNT_OFFSET)
91 io_rw_32 al2_transfer_count;
93 _REG_(DMA_CH0_AL2_READ_ADDR_OFFSET)
96 io_rw_32 al2_read_addr;
98 _REG_(DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET)
101 io_rw_32 al2_write_addr_trig;
103 _REG_(DMA_CH0_AL3_CTRL_OFFSET)
108 _REG_(DMA_CH0_AL3_WRITE_ADDR_OFFSET)
111 io_rw_32 al3_write_addr;
113 _REG_(DMA_CH0_AL3_TRANS_COUNT_OFFSET)
116 io_rw_32 al3_transfer_count;
118 _REG_(DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET)
121 io_rw_32 al3_read_addr_trig;
153 _REG_(DMA_INTR_OFFSET)
158 _REG_(DMA_INTE0_OFFSET)
163 _REG_(DMA_INTF0_OFFSET)
168 _REG_(DMA_INTS0_OFFSET)
175 _REG_(DMA_INTE1_OFFSET)
180 _REG_(DMA_INTF1_OFFSET)
185 _REG_(DMA_INTS1_OFFSET)
194 _REG_(DMA_TIMER0_OFFSET)
200 _REG_(DMA_MULTI_CHAN_TRIGGER_OFFSET)
203 io_wo_32 multi_channel_trigger;
205 _REG_(DMA_SNIFF_CTRL_OFFSET)
215 _REG_(DMA_SNIFF_DATA_OFFSET)
222 _REG_(DMA_FIFO_LEVELS_OFFSET)
227 io_ro_32 fifo_levels;
229 _REG_(DMA_CHAN_ABORT_OFFSET)