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rosc.h
1// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
2
8#ifndef _HARDWARE_STRUCTS_ROSC_H
9#define _HARDWARE_STRUCTS_ROSC_H
10
16#include "hardware/regs/rosc.h"
17
18// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_rosc
19//
20// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
21// _REG_(x) will link to the corresponding register in hardware/regs/rosc.h.
22//
23// Bit-field descriptions are of the form:
24// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
25
26typedef struct {
27 _REG_(ROSC_CTRL_OFFSET) // ROSC_CTRL
28 // Ring Oscillator control
29 // 0x00fff000 [23:12] ENABLE (-) On power-up this field is initialised to ENABLE +
30 // 0x00000fff [11:0] FREQ_RANGE (0xaa0) Controls the number of delay stages in the ROSC ring +
31 io_rw_32 ctrl;
32
33 _REG_(ROSC_FREQA_OFFSET) // ROSC_FREQA
34 // Ring Oscillator frequency control A
35 // 0xffff0000 [31:16] PASSWD (0x0000) Set to 0x9696 to apply the settings +
36 // 0x00007000 [14:12] DS3 (0x0) Stage 3 drive strength
37 // 0x00000700 [10:8] DS2 (0x0) Stage 2 drive strength
38 // 0x00000070 [6:4] DS1 (0x0) Stage 1 drive strength
39 // 0x00000007 [2:0] DS0 (0x0) Stage 0 drive strength
40 io_rw_32 freqa;
41
42 _REG_(ROSC_FREQB_OFFSET) // ROSC_FREQB
43 // Ring Oscillator frequency control B
44 // 0xffff0000 [31:16] PASSWD (0x0000) Set to 0x9696 to apply the settings +
45 // 0x00007000 [14:12] DS7 (0x0) Stage 7 drive strength
46 // 0x00000700 [10:8] DS6 (0x0) Stage 6 drive strength
47 // 0x00000070 [6:4] DS5 (0x0) Stage 5 drive strength
48 // 0x00000007 [2:0] DS4 (0x0) Stage 4 drive strength
49 io_rw_32 freqb;
50
51 _REG_(ROSC_DORMANT_OFFSET) // ROSC_DORMANT
52 // Ring Oscillator pause control
53 // 0xffffffff [31:0] DORMANT (-) This is used to save power by pausing the ROSC +
54 io_rw_32 dormant;
55
56 _REG_(ROSC_DIV_OFFSET) // ROSC_DIV
57 // Controls the output divider
58 // 0x00000fff [11:0] DIV (-) set to 0xaa0 + div where +
59 io_rw_32 div;
60
61 _REG_(ROSC_PHASE_OFFSET) // ROSC_PHASE
62 // Controls the phase shifted output
63 // 0x00000ff0 [11:4] PASSWD (0x00) set to 0xaa +
64 // 0x00000008 [3] ENABLE (1) enable the phase-shifted output +
65 // 0x00000004 [2] FLIP (0) invert the phase-shifted output +
66 // 0x00000003 [1:0] SHIFT (0x0) phase shift the phase-shifted output by SHIFT input clocks +
67 io_rw_32 phase;
68
69 _REG_(ROSC_STATUS_OFFSET) // ROSC_STATUS
70 // Ring Oscillator Status
71 // 0x80000000 [31] STABLE (0) Oscillator is running and stable
72 // 0x01000000 [24] BADWRITE (0) An invalid value has been written to CTRL_ENABLE or...
73 // 0x00010000 [16] DIV_RUNNING (-) post-divider is running +
74 // 0x00001000 [12] ENABLED (-) Oscillator is enabled but not necessarily running and stable +
75 io_rw_32 status;
76
77 _REG_(ROSC_RANDOMBIT_OFFSET) // ROSC_RANDOMBIT
78 // Returns a 1 bit random value
79 // 0x00000001 [0] RANDOMBIT (1)
80 io_ro_32 randombit;
81
82 _REG_(ROSC_COUNT_OFFSET) // ROSC_COUNT
83 // A down counter running at the ROSC frequency which counts to zero and stops.
84 // 0x000000ff [7:0] COUNT (0x00)
85 io_rw_32 count;
86} rosc_hw_t;
87
88#define rosc_hw ((rosc_hw_t *)ROSC_BASE)
89static_assert(sizeof (rosc_hw_t) == 0x0024, "");
90
91#endif // _HARDWARE_STRUCTS_ROSC_H
92
Definition rosc.h:26